1. Field of the Invention
The present invention relates to a method and circuitry for generating a clock. More particularly, it relates to a clock generating method and circuitry capable of switching between clock frequencies.
2. Description of the Prior Art
Phase locked loops or PLLs can generate a frequency-multiplied clock having either the same frequency as an input clock or a frequency that is an integral multiple of the frequency of the input clock, the frequency-multiplied clock being synchronized with the input clock. Recently-developed microprocessors operate on a high-speed clock such as a tens to hundreds of MHz clock and hence include a PLL as an indispensable component. On the other hand, recent years have seen progress made toward reducing power consumption in LSIs. Methods of reducing the clock frequency according to system operating conditions have been proposed as a technique for reducing power consumption.
Referring now to FIG. 7, there is illustrated a block diagram showing the structure of prior art clock generating circuitry capable of changing the frequency of its output. In the figure, reference numeral 1 denotes a PLL for generating a frequency-multiplied clock having either the same frequency as an input clock or a frequency that is an integral multiple of the frequency of the input clock, the frequency-multiplied clock being synchronized with the input clock, numeral 2 denotes a frequency dividing circuit for dividing the frequency of an output of the PLL 1 by a frequency dividing ratio corresponding to a frequency dividing ratio control signal applied thereto so as to generate a frequency-divided clock, numeral 3 denotes an output buffer for furnishing the frequency-divided clock from the frequency dividing circuit 2 as an external system clock, numeral 4 denotes a delay locked loop or DLL for delaying the frequency-divided clock generated by the frequency dividing circuit 2 by a fixed time interval corresponding to an output of a comparator 5 so as to generate an internal clock and adjust the phases of the external system clock and the internal clock, and numeral 6 denotes an internal circuit that operates on the internal clock. The comparator 5 compares the phase of a feedback clock from the internal circuit 6 and that of the external system clock and then furnishes a control signal to adjust the phases of the external system clock and the internal clock to the DLL 4.
In operation, the frequency dividing circuit 2 divides the frequency of the output of the PLL 1 by a frequency dividing ratio corresponding to the frequency dividing ratio control signal applied thereto so as to generate a frequency-divided clock. The clock generating circuitry can change the frequency of its output by controlling the frequency dividing ratio. The frequency dividing ratio control signal can be directly applied to the frequency dividing circuit 2 via an external terminal, or can be furnished to the frequency dividing circuit 2 by the internal circuit 6 controlled by the internal clock. As an alternative, the frequency dividing ratio control signal can be furnished by a circuit built on the same board, which operates on another clock that differs from the internal clock. The clock generating circuitry generates the internal clock supplied to the internal circuit 6 and the external system clock supplied to outside the chip from the frequency-divided clock from the frequency dividing circuit 2. The DLL 4 delays the frequency-divided clock by a fixed time interval corresponding to the control signal from the comparator 5 so as to generate the internal clock and also adjust the phase of the internal clock such that the internal clock is in phase with the external system clock.
Referring next to FIG. 8, there is illustrated a block diagram showing the structure of an example of the frequency dividing circuit 2 disposed in the prior art clock generating circuitry of FIG. 7. In the figure, reference numeral 21a denotes a 1/1th frequency divider 21a for dividing the frequency of the output of the PLL 1 by 1, numeral 21b denotes a 1/2th frequency divider for dividing the frequency of the output of the PLL 1 by 2, numeral 21c denotes a 1/4th frequency divider for dividing the frequency of the output of the PLL 1 by 4, numeral 21g denotes a 1/64th frequency divider for dividing the frequency of the output of the PLL 1 by 64, and numeral 21h denotes a 1/128th frequency divider for dividing the frequency of the output of the PLL 1 by 128. The frequency dividing circuit 2 further includes a 1/8th frequency divider, a 1/16th frequency divider, and a 1/32th frequency divider, which are not shown in the figure. In addition, reference numeral 22 denotes an edge trigger D-latch for furnishing a select signal to switch from a previously-selected one of a plurality of frequency-divided clocks generated by the plurality of frequency dividers 21a to 21h to a desired frequency-divided clock in response to the frequency dividing ratio control signal applied thereto from outside the frequency dividing circuit 2, and numeral 23 denotes a multiplexer for switching from a previously-selected one of the plurality of frequency-divided clocks of the plurality of frequency dividers 21a to 21h to a desired frequency-divided clock in response to the select signal from the edge trigger D-latch 22.
The frequency dividing circuit 2 can select one frequency-divided clock from the outputs of the 1/1th frequency divider 21a, the 1/2th frequency divider 21b, . . . , and the 1/128th frequency divider 21h, i.e., the 1/1th frequency-divided clock of the same frequency as the input clock, the 1/2th frequency-divided clock having a frequency that is a second submultiple of the frequency of the input clock, . . . , the 1/128th frequency-divided clock having a frequency that is a 128th submultiple of the frequency of the input clock, and then furnish the selected frequency-divided clock. In other words, the frequency dividing circuit 2 can freely switch from the 1/mth frequency-divided clock to the 1/nth frequency-divided clock, and vice versa, where m greater than n, and m=2, 4, . . . , 128 and n=1, 2, . . . , 64. In general, the plurality of frequency dividers 21a to 21h are so constructed that at the same time that the 1/128th frequency-divided clock from the 1/128th frequency divider 21h rises, all of the other frequency-divided clocks from the other frequency dividers 21a to 21g rise, and the edge trigger D-latch 22 furnishes the select signal that reflects a change in the frequency dividing ratio to the multiplexer 23 in response to a rising edge of the output of the 1/128th frequency divider 21h, so as to make the multiplexer 23 switch to a desired frequency-divided clock. The frequency dividing circuit 2 can thus change the frequency of its output smoothly without generation of spikes and glitches.
However, since the 1/1 to 1/128th frequency-divided clocks output from the plurality of frequency dividers 21a to 21h don""s always reach the multiplexer 23 at the same time because of unit-to-unit variation when manufacturing the frequency dividing circuit 2, and changes in the operating conditions such as ambient temperature and voltages, an undesirable clock pulse can be generated as follows when the multiplexer 23 switches between the 1/1 through 1/128th frequency-divided clocks. Referring next to FIG. 9, there is illustrated a timing chart showing an undesirable operation of the frequency dividing circuit 2 when the multiplexer 23 switches from the 1/2th frequency-divided clock to the 1/1th frequency-divided clock. Assume that the 1/1 and 1/2th frequency-divided clocks reach the multiplexer 23 at the expiration of Td1 and Td2, respectively, after the output of the PLL 1 is applied to the frequency dividing circuit 2. When switching from the 1/2th frequency-divided clock to the 1/1th frequency-divided clock, the frequency dividing circuit 2 generates a first clock pulse from the rising edge of a 1/2th frequency-divided clock pulse and the falling edge of a 1/1th frequency-divided clock pulse. Therefore, if the 1/2th frequency-divided clock reaches the multiplexer 23 slightly behind the 1/1th frequency-divided clock, that is, if Td1 less than Td2, because of unit-to-unit variation when manufacturing the frequency dividing circuit 2, or another cause, the first clock pulse generated when the multiplexer 23 switches from the 1/2th frequency-divided clock to the 1/1th frequency-divided clock has a shorter pulse width than any 1/1th frequency-divided clock pulse by (Td2xe2x88x92Td1). Similarly, when the multiplexer 23 switches from the 1/nth (n=4, 8, 16, 32, 64, 128) frequency-divided clock to the 1/1th frequency-divided clock, the first clock pulse generated when the multiplexer 23 performs the switching operation has a shorter pulse width than any 1/1th frequency-divided clock pulse by (Tdnxe2x88x92Td1) if Td1 less than Tdn.
A problem with prior art clock generating circuitry is thus that the first clock pulse generated when performing a switching operation can have a shorter pulse width than a given pulse width, and, when switching to the highest frequency, the first clock pulse generated when performing the switching operation can have a shorter pulse width than any 1/1th frequency-divided clock pulse corresponding to the highest operating speed of the device and therefore the device falls in dire straits so that it can malfunction.
The present invention is proposed to solve the above problem. It is therefore an object of the present invention to provide a method and circuitry for generating a clock, capable of, even when switching to any clock frequency, making the first clock pulse generated when performing the switching operation have a longer pulse width than any 1/1th frequency-divided clock pulse corresponding to the highest operating speed of the device.
In accordance with one aspect of the present invention, there is provided a clock generating method comprising the steps of: dividing the frequency of an input clock by each of a plurality of predetermined frequency dividing ratios differ from each other so as to generate a plurality of frequency-divided clocks in such a manner that a frequency-divided clock generated with the smallest frequency dividing ratio, i.e., a frequency-divided clock having the highest frequency is delayed slightly against all of the other frequency-divided clocks generated; and, when changing the frequency of an output clock, switching from a previously selected one of the plurality of frequency-divided clocks generated to a desired one of them, and furnishing the desired frequency-divided clock as the output clock.
In accordance with a preferred embodiment of the present invention, the dividing step includes the step of generating the plurality of frequency-divided clocks in such a manner that the frequency-divided clock having the highest frequency is delayed slightly against all of the other frequency-divided clocks generated under all conditions. Preferably, the dividing step includes the step of generating the plurality of frequency-divided clocks in such a manner that all but the frequency-divided clock having the highest frequency are in phase with each other and only the frequency-divided clock having the highest frequency is delayed. In addition, the generating step can include the step of delaying only the frequency-divided clock having the highest frequency such that a difference between the instant when the frequency-divided clock having the highest frequency is generated and the instant when any other frequency-divided clock is generated is less than a pulse width of pulses of the frequency-divided clock having the highest frequency.
In accordance with another preferred embodiment of the present invention, the generating step is the step of generating the plurality of frequency-divided clocks in such a manner that they are sequentially generated and are therefore shifted from each other in time in order of decreasing frequency dividing ratio, i.e., increasing frequency. Preferably, the generating step includes the step of delaying each of the plurality of frequency-divided clocks by a time interval that increases with decrease in the frequency dividing ratio set to generate each of the plurality of frequency-divided clocks, i.e., increase in the frequency of each of the plurality of frequency-divided clocks. Furthermore, the delaying step can be the step of delaying the plurality of frequency-divided clocks such that a difference between the instant when a 1/mth frequency-divided clock having an mth submultiple of the frequency of the input clock is generated and the instant when a 1/nth frequency-divided clock having an nth submultiple of the frequency of the input clock is generated, where m and n are different integers, is less than an absolute value of a difference between a pulse width of pulses of the 1/mth frequency-divided clock and that of the 1/nth frequency-divided clock.
In accordance with another aspect of the present invention, there is provided clock generating circuitry comprising: a frequency dividing unit for dividing the frequency of an input clock by each of a plurality of predetermined frequency dividing ratios differ from each other so as to generate a plurality of frequency-divided clocks, and for furnishing the plurality of frequency-divided clocks in such a manner that a frequency-divided clock generated with the smallest frequency dividing ratio, i.e., a frequency-divided clock having the highest frequency is delayed slightly against all of the other frequency-divided clocks generated; and a switching unit, responsive to a control signal, for switching from a previously selected one of the plurality of frequency-divided clocks furnished from the frequency dividing unit to a desired one of them and for furnishing the desired frequency-divided clock so as to change the frequency of an output clock.
In accordance with a preferred embodiment of the present invention, the frequency dividing unit generates the plurality of frequency-divided clocks in such a manner that the frequency-divided clock having the highest frequency is delayed slightly against all of the other frequency-divided clocks generated under all conditions. Preferably, the frequency dividing unit generates the plurality of frequency-divided clocks in such a manner that all but the frequency-divided clock having the highest frequency are in phase with each other, and includes a delay unit for delaying only the frequency-divided clock having the highest frequency and furnishing the delayed frequency-divided clock to the switching unit. In addition, the delay unit can delay only the frequency-divided clock having the highest frequency such that a difference between the instant when the frequency-divided clock having the highest frequency is generated and the instant when any other frequency-divided clock is generated is less than a pulse width of pulses of the frequency-divided clock having the highest frequency.
In accordance with another preferred embodiment of the present invention, the frequency dividing unit generates and furnishes the plurality of frequency-divided clocks in such a manner that they are sequentially generated and are therefore shifted from each other in time in order of decreasing frequency dividing ratio, i.e., increasing frequency. Preferably, the frequency dividing unit includes a delay unit for delaying each of the plurality of frequency-divided clocks by a time interval that increases with decrease in the frequency dividing ratio set to generate each of the plurality of frequency-divided clocks, i.e., increase in the frequency of each of the plurality of frequency-divided clocks. Furthermore, the delaying unit can delay the plurality of frequency-divided clocks such that a difference between the instant when a 1/mth frequency-divided clock having an mth submultiple of the frequency of the input clock is furnished to the switching unit and the instant when a 1/nth frequency-divided clock having an nth submultiple of the frequency of the input clock is furnished to the switching unit, where m and n are different integers, is less than an absolute value of a difference between a pulse width of pulses of the 1/mth frequency-divided clock and that of the 1/nth frequency-divided clock.
Further objects and advantages of the present invention will be apparent from the following description of the preferred embodiments of the invention as illustrated in the accompanying drawings.